-------------------------
-- 【触发器】
-- 只有在时钟脉冲的上升沿或下降沿的瞬间，输出才会跟随输入（又称触发）变化
-------------------------


-- en出现上升沿时，输出跟随输入变化
process(en)
begin
    if (en = '1') then
        q <= d;
    end if;
end process;


-- 变换1
process(clk, d)
begin
    if (clk = '1' and clk'evnet) then
        q <= d;
    end if;
end process;

-- 变换2
process
begin
    wait until clk = '1';
    q <= d;
end process;

-- 变换3
process(en)
begin
    case en is
        when '1' => q <= d;
        when others => null;
    end case;
end process;


-- 触发器对信号的传递延迟 (三级时钟延迟，延迟三个时钟周期)

library ieee;
use ieee.std_logic_1164.all;

entity delay is
    port(
        a, clk : in std_logic;
        q1, q2, q3 : in std_logic
    );
end delay;

architecture rtl of delay is
    signal qn, q2, q3 : std_logic;
begin
    
    process(clk)
    begin
        if clk'event and clk = '1' then
            qn <= a;    -- 1
            qn1 <= qn;  -- 2
            qnm <= qn1; -- 3
        end if;        
    end process;

    q3 <= qnm;
    q2 <= qn1;
    q1 <= qn;

end rtl;
